1. Field of the Invention
The present invention relates to the field of display technology, and in particular to an array substrate and a manufacturing method thereof.
2. The Related Arts
In the field of display technology, the flat panel display techniques have gradually taken the place of cathode ray tube (CRT) display devices. The flat panel display devices have various advantages, such as high image quality, low power consumption, thin device body, and wide applications, and are thus widely used in various consumer electronics, such as mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, and desktop computers and become the mainstream of display devices.
A thin-film transistor (TFT) is a primary driving component of conventional liquid crystal displays (LCDs) and active matrix organic light-emitting diode (AMOLED) displays and has a direct influence on the direction of development of high quality flat panel display devices. There are various structures available for thin-film transistors and there are also various materials that can be used to make the corresponding structures of the thin-film transistors. Among such materials, LTPS (low temperature poly-silicon) is a preferred one. Due the regular arrangement of atoms, LTPS has high carrier mobility, making it possible to drive the rotation of liquid crystal molecules with a size-reduced thin-film transistor thereby reducing, to quite an extent, the space occupied by the thin-film transistor, increasing the area for light transmission, and thus providing greater brightness and resolution. For current-driving active matrix driving organic electroluminescence displays, LTPS TFT may better suit the requirements for driving current.
Thus, LTPS TFT based display panels are favored by the general consumers due to excellent high image quality, high resolution, being ultra thin and light, and low power consumption. The LTPS techniques are gradually taking the place of the conventional amorphous silicon (a-Si) TFT techniques to become the mainstream of the next generation display technology. However, the conventional processes for manufacturing LTPS array substrates are generally complicated and the manufacturing costs are high.
As shown in FIG. 1, a conventional complementary metal oxide semiconductor (CMOS) LTPS TFT array substrate comprises a base plate 110, a light shielding layer 120 formed on the base plate 110, a buffer layer 130 formed on the base plate 110 and the light shielding layer 120, an active layer 140 formed on the buffer layer 130, a gate insulation layer 150 formed on the buffer layer 140, a gate electrode 160 formed on the gate insulation layer 150, an interlayer insulation layer 170 formed on the gate electrode 160, source/drain electrodes 180 formed on the interlayer insulation layer 170, a planarization layer 190 formed on the source/drain electrodes 180, a common electrode 200 formed on the planarization layer 190, an insulation layer 210 formed on the common electrode layer 200, and a pixel electrode 220 formed on the insulation layer 210. FIG. 2 is a top plan view of the CMOS LTPS array substrate of FIG. 1, in which the common electrode 200 is a planar electrode of a complete surface. Thus, a conventional process for manufacturing a CMOS LTPS TFT array substrate, after the formation of the gate electrode 160, must form an interlayer insulation layer 170 to function as insulation between the gate electrode 160 and the source/drain electrodes 180. The manufacturing process is complicated and the manufacturing cost is high.